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[VHDL-FPGA-Verilog] fir

Description: 用VHDL语言设计有限脉冲响应的FIR滤波器。用户可以在Xilinx ISE环境下运行。-With VHDL language design finite impulse response of FIR filter. Users can run Xilinx ISE environment.
Platform: | Size: 470016 | Author: chenlan | Hits:

[VHDL-FPGA-Verilog] FIR

Description: 采用vhdl语言 设计FIR滤波器，经调试好使，献给广大硬件开发的朋友参考学习-FIR filter design using vhdl language, so that upon commissioning, the development of friends dedicated to the general hardware reference learning
Platform: | Size: 8192 | Author: youlijun | Hits:

[VHDL-FPGA-Verilog] FIR-LOOP-

Description: 数字接收机中的FIR滤波器，环形滤波器设计参考,VHDL代码-the FIR filter， loop filter design in a digital receiver,vhdl code
Platform: | Size: 1024 | Author: rickdecent | Hits:

[VHDL-FPGA-Verilog] fir-filter

Description: fft的vhdl实现源代码，具体的有心情有兴趣的可以自己下载下来看下，因为我也是在入门中不懂。-fft verilog HDL
Platform: | Size: 7241728 | Author: liu | Hits:

[VHDL-FPGA-Verilog] FIR_cautruc_truc_tiep

Description: this is FIR filter by VHDL
Platform: | Size: 1024 | Author: thuyhang | Hits:

[VHDL-FPGA-Verilog] FIR-filter-VHDL-code

Description: 基于FPGA的17阶FIR滤波器VHDL代码。文件附带了FIR数字滤波器理论的介绍。-FPGA-based 17-order FIR filter VHDL code. File with the FIR digital filter theory introduction.
Platform: | Size: 919552 | Author: 周鑫 | Hits:

[VHDL-FPGA-Verilog] vhdl_fir

Description: 这是一个vhdl语言写的fir filter，包括receiver, filter, transfer,可用于驱动fpga等板子-this is a fir filter use VHDL language, include receiver, filter, transfer. can be used to drive fpga and some else boards
Platform: | Size: 258048 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] VHDL

Description: 基于FPGA的IIR滤波器的各模块VHDL程序- such as in science and project technique. Compared with FIR digital filter, IIR digital filter can get high selectivity with low factorial.
Platform: | Size: 1024 | Author: 许成 | Hits:

[VHDL-FPGA-Verilog] 26352153-VHDL-Coding-for-FIR-Filter

Description: VHDL filter design powerpoint
Platform: | Size: 560128 | Author: HIDIR | Hits:

[VHDL-FPGA-Verilog] FIR---ALEX

Description: Filter c language, better validation, able to run the filter C language-FIR filter VHDL, you can use, though a bit......
Platform: | Size: 8329216 | Author: 许震 | Hits:

[Other] filter

Description: 各种模块实现10阶FIR滤波器,用matlab中的fdatool计算出设计的滤波器的系数，再利用VHDL编写各模块程序，实现滤波器-Various modules to achieve the10order filter based on FIR, using MATLAB FDATool calculates the design of the filter coefficients, then use VHDL to prepare procedures for each module, the realization of filters
Platform: | Size: 289792 | Author: 刘定超 | Hits:

[OS program] FIR

Description: an FIR code which is writen in vhdl. this entity has clk and reseet inputs, and the filter output is provided as well. the coefficients of the filter are passed using a set of constants.
Platform: | Size: 3072 | Author: mohandes | Hits:

[VHDL-FPGA-Verilog] filter

Description: 基于VHDL的FIR数字滤波器的设计，可以自己修改参数设置滤波器阶数-FIR digital filter design based on VHDL, can modify the parameters to set the filter order
Platform: | Size: 1860608 | Author: 123 | Hits:

[VHDL-FPGA-Verilog] FIR

Description: fir数字滤波器，VHDL语言编程，先通过MATLAB计算得到参数。-fir digital filter VHDL language programming, first obtained by MATLAB calculated parameters.
Platform: | Size: 946176 | Author: jinhong | Hits:

[VHDL-FPGA-Verilog] fir

Description: 利用VHDL和Verilog HDL语言实现FIR滤波器-Using VHDL and Verilog HDL language to realize FIR filter
Platform: | Size: 49152 | Author: 姚远 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 该程序实现了一个FIR滤波加速器，该程序在FPGA板上开发，通过使用VHDL语言来定义RS232端口的使用-design a FIR Filter Accelerator based on FPGA board and RS232 interface using VHDL language.
Platform: | Size: 593920 | Author: 浦馨 | Hits:

[Other] fir

Description: 本历程是用 VHDL实现fir滤波器cds算法的历程，熟悉CDSsuanfa -This process is to achieve fir filter algorithm cds course, familiar with CDSsuanfa
Platform: | Size: 633856 | Author: 恩飞 | Hits:

[Software Engineering] FIR-filter-vhdl

Description: FIR数字滤波器设计，用VHDL来实现，用quarsII软件实现其功能-FIR FILTER vhdl
Platform: | Size: 656384 | Author: 汪良伟 | Hits:

[VHDL-FPGA-Verilog] filter_lpm_shaping

Description: 4倍内插值的fir成型滤波器，语言vhdl，工程已建立，可以直接运行-4x interpolation of fir shaping filter, language vhdl, project has been established, you can directly run
Platform: | Size: 16975872 | Author: chen | Hits:

[VHDL-FPGA-Verilog] FIR-filter

Description: VHDL设计的FIR滤波器，由3个文件组成：FIR.VHD、PACK.VHD和signed.vhd。testfir.vhd为测试平台。-VHDL designed FIR filters, composed by the three documents: FIR.VHD, PACK.VHD and signed.vhd. The testfir.vhd is a testbench.
Platform: | Size: 8192 | Author: 叶宗英 | Hits:
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